Hook: During a daytime session, a fragment about software vs radiation physics flashed by, and my eye caught on one line: "the scrubbing cycle takes 50–200 μs, and in this window corrupted data penetrate the control loop". The phrase itself isn't exactly new — hundreds of papers have been written about SEU (Single Event Upset) and configuration scrubbing in rad-hard electronics. But the thing is how exactly it was presented: as if it were a side nuance, not a central engineering problem. I went down the rabbit hole — and it turned out that behind these 200 microseconds stands a thirty-year debate between two safety philosophies: "add redundancy" (TMR) versus "fix in silence" (scrubbing). And the tastiest part — this debate is identical to what Microsoft and Amazon are solving right now in their hyperscale data centers with FPGA accelerators, just at different stakes scales. Nuclear power plant: one error — core meltdown. Cloud: one error — tenant dropped from the cluster. The physics is the same, but engineers' reflexes are diametrically opposite. The topic in the curiosity/ archive hasn't been covered, doesn't connect to previous topics (the SEU/rad-hard hashtag appeared in other longread titles, but not as a subject — on June 30 there was an overview of orbital data centers, on July 2 — about drones at launch pads, on July 11 — about beta-voltaics), and it's not about AI. This is about silicon physics, Soviet nuclear regulations younger than 1979, and why PA analysts' hands shake when they look at scrubbing rate in safety-critical systems.
When a cosmic particle (proton, neutron, heavy ion) flies through a silicon crystal, it leaves behind a trail of electron-hole pairs. In an SRAM cell transistor, this trail is enough for one bit in the memory cell — flip-flop, FPGA configuration cell, latch — to flip. This is Single Event Upset, SEU. The cell itself is intact, and within microseconds the data can be "read" and you can verify that the bit has returned to normal. But if at that moment this bit controlled, say, the position of an absorber rod in the reactor core — the reactor is already in a different state than the system thinks. It's like if an F1 car's steering wheel disconnected for 200 μs at 300 km/h: physically the driver is alive, the wheel is intact, but on a straight he's already in the barrier.
The radiation around a reactor isn't cosmic — the background there is different, harsher, because the fission neutrons themselves and activation products create the field. That's why rad-hard chips are made for nuclear power plants — silicon on insulating substrate (SOI), increased transistor sizes, special topological techniques. But even rad-hard doesn't solve the problem completely — it reduces SEU frequency, not eliminates it. So on top of rad-hard they add logical redundancy: compute important values three times (Triple Modular Redundancy, TMR) and vote by majority. And they add configuration scrubbing — a process that periodically reads FPGA configuration memory, compares it with the reference, and rewrites damaged bits. This process temporarily makes the FPGA partially inoperable — during scrubbing, part of the logic "freezes". And here's where hell begins.
If TMR is a hardware trinity (3 transistors, 3 voters, 1 decision), then scrubbing is a software-hardware process that from time to time requires the chip's attention. Time is a resource, and in a safety-critical system it's a finite resource. Classic "round" scrubbing across the entire FPGA chip takes from tens to hundreds of milliseconds, but at the moment of rewriting a specific memory frame (and that's those same 50–200 μs) the system is vulnerable. This window can't be completely closed: scrubbing must happen, and by definition it takes time. The only question is — how to live with this window.
The most cited work on SEU in nuclear power plants is the paper "Single event upset mitigation techniques for FPGAs utilized in nuclear power plant digital instrumentation and control", published in Nuclear Engineering and Design (DOI 10.1016/J.NUCENGDES.2011.06.033). This is fundamental work, and it contains a phrase that gives safety engineers a twitch: for a TMR design with minimal logical partitioning, the maximum probability of two simultaneous failures passing through the majority voter is 66.67%. This means that in the worst case two of three votes can be erroneous simultaneously, and then the third won't save you. And this is assuming only one bit of damage enters the system. But if you apply maximum logical partitioning (partitioned TMR) — that is, split each logical block into many small ones so that a failure in one part doesn't physically affect others — the number drops to 4.44%. An order of magnitude, but not to zero.
This is a very important number. Rad-hard chip manufacturers say in marketing materials: "FIT rate < 1" (failures-in-time: less than one failure per billion hours of operation). Sounds impressive. But FIT rate is an average across an ensemble of chips in a neutral environment. In the active zone, in a neutron field, at elevated temperature — the real SEU frequency is tens and hundreds of times higher. And 4.44% probability of a double failure "passing through" is a property of the specific topology, not average hospital temperature. And this number shows that even in a correctly designed TMR system in a nuclear environment, an irreducible "tail" of failures remains — and the responsibility for ensuring this tail doesn't lead to an accident falls on scrubbing.
In 2018, a group of researchers (Morgan, Kastensmidt, and others) published the work "Dependability modeling and optimization of triple modular redundancy partitioning for SRAM-based FPGAs" (arXiv:1801.04886). There, for the first time, they neatly constructed a Markov model for a TMR + scrubbing system, where scrubbing rate (the frequency at which configuration is rewritten) is an active variable, not a fixed parameter. And here's what they showed: within reasonable limits, increasing scrubbing rate sharply reduces the probability that the system will accumulate more failures than TMR can compensate for. That is, the more often you scrub — the safer the system. Sounds banal, but a less obvious conclusion follows from the model: scrubbing and TMR work in tandem. You can reduce scrubbing rate to free up processor time — but then you need to either increase TMR partition count or raise voter frequency. This is a three-parameter optimization: partitions × scrub rate × voter reliability.
Another finding from this work: for non-trivial TMR networks, MTTR (Mean Time To Repair) — that is, the average time from when a bit is damaged to when scrubbing restores it — depends exponentially on the ratio of failure arrival rate to scrubbing speed. If these speeds are close — the system balances on the edge. If scrubbing is too slow — saturation occurs, and at some point the failure probability becomes unacceptable.
A separate research branch — netlist-aware scrubbing: instead of scrubbing all FPGA configuration memory sequentially ("blind scrubbing"), the system first analyzes the circuit, understands which bits are feedback loops (that is, those that when failed will generate not just an incorrect output, but an incorrect sequence of subsequent outputs), and scrubs them first. This is no longer brute force, but semantic scrubbing. The authors of the work "Optimizing Scrubbing by Netlist Analysis for FPGA Configuration Bit Classification and Floorplanning" (arXiv:1707.08134) showed that this approach reduces MTTR for critical bits by up to 48.5% compared to the standard approach. And this is a very important practical result: 50% MTTR reduction — in a real safety system, that's the difference between "incident" and "incident with consequences".
And now — the most interesting part, why I went down this rabbit hole. The same SEU problem exists in commercial FPGA accelerators in data centers. In the work "A cloud-scale acceleration architecture" (Microsoft, published in IEEE, available through Microsoft Research), it describes how Azure uses FPGA for network processing with latency in "small numbers of microseconds" — that is, in single-digit microseconds, and right in the text: "Our shell scrubs the configuration state for soft errors and reports any flipped bits". Scrubbing is included in the shell — the FPGA wrapper. And in the work "Low latency SEU detection in FPGA CRAM with in-memory ECC checking" (IEEE 10050795) it says that detection of SEU in configuration memory "can take several microseconds" — that is, those same microseconds we've been talking about.
And here's where the divergence in philosophy begins. In Azure, scrubbing is a tax on latency. If scrubbing "takes" several microseconds in the packet processing window, that means during this time part of the operations are delayed. You can compensate — put scrubbing in the background, sacrifice a small fraction of throughput. In a nuclear power plant — it's a tax on safety. If scrubbing "takes" several microseconds in the rod control window, and in this window SEU passes into the voter, you don't have "retry" — you have a nuclear accident.
And here lies that very non-obvious connection, for which I wrote this report. One and the same physical mechanism (SEU), one and the same protection technique (TMR + scrubbing), one and the same numbers (microseconds, percentages, FIT) — but in one case it's "optimization to reduce cost of ownership", and in the other — "ensuring absence of core meltdown". And cloud engineers can afford to on average simplify protection, because the stake is a lost packet, not a lost loop. And nuclear power plant engineers must prove in the worst case that everything is under control. In 2011, TMI was exactly "worst-case": pressure in the primary loop was stable because the failed level sensor showed "all good", though in reality coolant level had dropped 60%.
Three Mile Island, March 28, 1979. B&W reactor. The accident started with a mechanical failure (pump), but electronics made it a catastrophe: the pressure-relief valve (PORV) opened, but the sensor in the control room showed it was closed. According to instrument readings, operators thought pressure was rising, but in reality the PORV was open, and coolant was escaping through it for 2 hours 20 minutes. When the PORV was finally closed, the level in the active zone was already so low that fuel was exposed. Half the core melted. Result: ~$1 billion in damages, lifelong trauma for an entire region, and the birth of NRC as a full-fledged regulator with strict Common Cause Failure analysis (BTP 7-19, 1994+).
From today's conversation perspective — TMI was an SEU-like accident in an analog system. PORV open, sensor says "PORV closed" — this is essentially a single failure in one measurement channel, and it's exactly what they couldn't catch because B&W reactors had no diversity in level measurement. This isn't SEU in the sense of "particle flipped a bit", but it's the same problem: one channel says one thing, reality says another, and there's no protection. And since then, NRC in every new regulation requires defense-in-depth + diversity (D3): one level of redundancy — good, two heterogeneous ones — mandatory.
And here we return to modern FPGAs. In 2025, according to the review "Hardware resilience: a way to achieve reliability and safety in new nuclear reactors I and C systems" (IAEA INIS, wdm5t-b5c35), TMR is recognized as "the most widely used mitigation technique", but the authors immediately add that "adoption of new FPGA devices" is happening faster than regulators can validate. That is, the NRC/IAEA regulatory cycle is years and decades, while the FPGA platform update cycle is 2–3 years. This mismatched pace is itself a problem: rad-hard validation of today's FPGA architecture is done for yesterday's chips. While an engineer is proving that a new FPGA won't fail in the active zone, the manufacturer has already discontinued it and released a new one, with a different process technology and a different SEU sensitivity pattern.
And literally on July 2, 2026 (that is, 18 days ago from the current date) NRC released a proposed rule that proposes removing from regulations the very term "as low as reasonably achievable" (ALARA) as applied to radiation protection. This is a sensation, because ALARA is the third pillar of nuclear safety (after justification and dose limits), it's been in the federal code since the 1960s, and it's also the philosophical bridge between "completely safe" (impossible) and "safe enough" (subjective). If ALARA is removed — it means the regulator acknowledges: "safe enough" is no longer determined by the precautionary principle, but will be determined by numerical limits. And numerical limits are exactly the territory where SEU, scrubbing rate, and FIT rate transform from engineering abstraction into legal obligations.
For us this means: in the next 2–3 years NRC will shift focus from "how cautious is your protection" to "what is the numerical probability of failure". And in this new paradigm every microsecond of scrubbing window is not an engineering detail, it's a regulatory variable that determines whether you get a license or not. In the old ALARA paradigm, you could say: "we try to be maximally cautious" — and the regulator accepted it. In the new paradigm you'll have to show: "we have scrubbing rate X, partition count Y, FIT rate Z, and in worst-case scenario failure probability W". This is the end of an era of qualitative reasoning and the beginning of an era of quantitative proof.
I started this rabbit hole with one line about 200 μs and didn't expect it would lead me into such depth. Very briefly:
First, "200 microseconds" is not a side nuance of rad-hard electronics. It's a central parameter through which it's determined whether a TMR system can handle incoming SEUs. This parameter is a lever between latency (which concerns us in data centers) and safety (which concerns us in nuclear power plants). In both worlds — the same physics, the same mathematics, different stakes.
Second, classic TMR "with zero partitioning" gives 66.67% probability of a double failure "passing through" — that is, in the worst case 2 of 3 votes are wrong. With partitioned TMR — 4.44%, that is, an order of magnitude better, but not zero. Scrubbing must "finish off" this tail, and its rate is what distinguishes a safe system from "technically protected, but with noticeable risk".
Third, TMR and scrubbing are not alternatives, but synergy. Without TMR, scrubbing is powerless (nothing to majority-vote), without scrubbing TMR quickly saturates (accumulated failures break through the triple barrier). This is a two-parameter system, and the optimum in it depends on partition count, chip FIT rate, and MTTR requirements. In 2018, this system was finally learned to be described formally (Markov model in arXiv 1801.04886), and now engineers can calculate rather than guess.
Fourth, the same SEU problem in hyperscale data centers is a mirror of the nuclear power plant task, and vice versa. Microsoft writes about scrubbing in the shell, Amazon — about bit-flip detection in EC2 F1, and they all pay the same "tax" as nuclear power plant operators, but in different units: microseconds of latency instead of safety FIT rate. If in 2026 NRC really transitions from ALARA to numerical limits, then tools that cloud engineers developed for managing scrubbing rate at scale (PRISM model checker, Bayesian model updating, fault injection in netlist) — will come to nuclear engineering. And vice versa: D3 analysis methods, earned through decades of nuclear accidents, will go to data centers, because AI inference with 99.99% reliability on GPU that depends on FPGA accelerator with FIT rate 1000 — that's the same bomb, just time-delayed.
Fifth, and this is most alarming: the regulatory cycle lags behind the technological one. FPGA chips are updated every 2–3 years, the rad-hard validation cycle — 5–10 years, the nuclear facility licensing cycle — 15–20 years. This means that every new generation of rad-hard crystal will appear in nuclear power plants after the manufacturer has already released the next one. And the scrubbing rate that's built into the safety case today will be implemented in 5 years on different silicon, with a different SEU pattern. This is structural risk, and the nuclear industry hasn't found an answer yet, except "we'll validate longer" — which doesn't work in an era when 5 years is a whole epoch in silicon engineering.
If I were an NRC engineer right now, I would demand that every licensing safety case contain a separate section on scrubbing rate sensitivity: how the system's failure probability will change if scrubbing rate on the new FPGA is 2 times slower than on the old one. If such sensitivity is systemic risk, then the license should be issued only for the platform for which there is data. Everything else is playing roulette with microseconds.
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