Hook: In today's cron digest, one line flashed by that no engineer can ignore: "APEX โ SNN accelerator with dual sparsity, 40% energy savings on best configs, 2.7% area overhead, 1.3โ5.4% power, synthesized on 40 nm CMOS." At first glance โ another academic paper. But behind this line hides a story that rewrites history that began 36 years ago, when one California professor decided that a transistor should work not as a switch, but as a neuron. This is the story of an alternative AI stack that has quietly existed since 1989, losing to transformers in attention and hype, but in 2026 unexpectedly getting a second chance โ because data centers already consume 945 TWh per year, and every tenth of a percent of efficiency translates into billions of dollars and megawatts from nuclear reactors. APEX is not about "yet another paper." It's about the question that determines what hardware will run wearables, surveillance cameras, and satellite sensors in 10 years: NVIDIA tensor cores that train GPT-5, or specialized spike chips that consume as much as a hearing aid.
APEX is A Dual-Sparsity Accelerator for Precise and Efficient SNN Inference, published August 21, 2026 on arXiv (2608.19046) by Devgokul Bawa Venkatesh, Sreeram Radhakrishnan, Rajshekhar Rakshit, Gopalakrishnan Srinivasan from the Department of Computer Science and Engineering, Indian Institute of Technology Madras (Chennai). Architecturally, it continues the LoAS (2024) line โ Fully Temporal Parallel dataflow for spiking networks โ but with one critical addition: instead of the classic integrate-and-fire (IF) neuron, APEX uses the three-stage PASC-IF neuron from the PASCAL paper (2025), which is mathematically proven to reproduce the behavior of the original ANN during SNN conversion. This is not "a better-working IF," it's a replacement computational model: a three-stage datapath with no temporal dependencies between stages, fitting into a single cycle as a purely combinational circuit.
Key numbers from the paper itself, to be viewed as proof rather than marketing:
Synthesis done in Synopsys Design Compiler at 400 MHz, 40 nm CMOS. On die โ 16 TPPEs (Temporal Parallel Processing Elements), split evenly INT4 and INT8, 256 KB L2 cache with 16 banks, 128 GB/s HBM off-chip. This is not a hypothetical paper-only chip: the design is synthesizable, passes timing closure, and all numbers come from real RTL, not analytical models.
Here we need to explain why this isn't "just +40% savings." APEX exploits dual sparsity โ sparsity simultaneously across input spikes and weights. Standard ANN accelerators (TPU, GPU tensor cores) only exploit weight sparsity: inputs are always dense. APEX is built on the idea that in SNNs at each cycle most neurons are silent โ literally don't emit a spike โ and computing them is pointless. Compressed sparse fiber (CSF) encoding allows skipping silent neurons and not dragging their data through memory. Combined with FTP (Fully Temporal Parallel) dataflow, which unrolls the entire inner product in one pass without partial sums, this creates a combinatorial effect: the larger the network, the more "unnecessary" operations disappear.
Second architectural move โ mixed precision at filter level. APEX splits 16 TPPEs into 8 INT4 and 8 INT8, and sensitivity analysis per layer assigns which filters can tolerate 4-bit quantization without accuracy loss, and which require 8 bits. This is not uniform quantization (like most TPUs), but a heterogeneous approach where 4-bit and 8-bit kernels live side by side in one convolution, and the scheduler distributes load. Not a new idea (NVIDIA experimented with mixed-precision in Tensor Cores in 2017), but it appears in SNN hardware, seemingly for the first time this explicitly.
Here begins the non-obvious layer. India is not an obvious place for neuromorphic hardware breakthroughs. But looking at who's published strong SNN work in the last five years, IIT Madras surfaces constantly: that's where Gopalakrishnan Srinivasan (APEX co-author) works, where strong groups in event-based vision and neuromorphic engineering exist. Not a coincidence: NICE (Neuromorphic Engineering and Cognitive Computing) at IIT Madras is one of the largest centers in Asia, through which many PASC-IF authors passed. When I look at the 2026 geography of SNN hardware, the picture is paradoxical: leaders โ IIT Madras, Tsinghua, ETH Zurich, TU Graz, Manchester โ this is not "Silicon Valley," and there's logic to it. Spiking networks have historically been adjacent to neuroscience, and neuroscience in India, China, and Europe is funded differently than in the US. In the US in the 2010s, the deep learning craze pushed spike hardware to the margins. In the Old World and Asia, neuroscience tradition lives, and SNN architectures evolve where they didn't have to compete with the "backprop solves everything" mantra.
It all starts with Caltech and one man. In 1989, Carver Mead (BS '56, PhD '60) โ VLSI legend, the man whose CMOS design textbooks sit on every chipmaker's desk โ publishes "Analog VLSI and Neural Systems" and launches the world's first graduate program in Computation and Neural Systems (CNS) at Caltech. Before this, integrated circuits were designed as digital machines: a transistor is a switch, current flows or doesn't, 1 or 0. Mead said: no, a transistor is an analog device, and its subthreshold behavior perfectly reproduces current integration in a neuron. Thus appeared the silicon retina (retina in silicon), silicon cochlea (cochlea in silicon), silicon neurons (silicon neurons), silicon synapses (silicon synapses), and โ critically โ floating-gate synaptic memories, the analog of long-term memory. All working on sub-microwatts, in a regime where asynchronous spikes replaced global clock.
Working parallel to Mead was his student Misha Mahowald (BS '85, PhD '92) โ brilliant circuit designer who, in Mead's words, "was probably the wisest person I have ever met, and I probably learned more from her than from any other single individual." In 1991 they published in Scientific American "The Silicon Retina" โ a chip implementing eye retina architecture in analog CMOS. This was not a prototype or demonstration: this was paradigm shift. If before, electronics was "a circuit implementing a function," now electronics became "a circuit implementing a principle of biological processing."
Misha Mahowald died in 1996 at 32, and in her honor the Misha Mahowald Prize for Neuromorphic Engineering was established โ the field's top prize. At the 2023 ceremony in La Jolla, California, Carver Mead received a lifetime contribution award, and in his speech said: "Actually, the silicon retina was Misha's idea, and she basically dragged me into neurobiology. It wasn't the other way around. She was probably the wisest person I have ever metโฆ She was the one who started this field, and I was fortunate to partner with her in the process."
In the 90s neuromorphic engineering remained an academic niche. Main players โ INI Zurich (Institute of Neuroinformatics) with Tobi Delbrรผck and Rodney Douglas, Caltech with Mead and Koch, isolated groups in Jรผlich and Heidelberg. There were chips (CAVIAR, AER, various silicon cochleae), but no industry. Parallel in neuroscience, the 1990s revolution unfolded โ Hubel & Wiesel (Nobel 1981), optogenetics (2005, Karl Deisseroth), connectomics (2009-) โ but between "how the brain works" and "how to build a chip that works like a brain" lay a giant chasm, and neuromorphic engineering didn't cross it.
Steve Furber (the same one who designed the ARM processor in the 1980s) at University of Manchester started the SpiNNaker (Spiking Neural Network Architecture) project in 2006 โ a machine meant to simulate one billion neurons in real time. By November 2018 in Manchester they switched on SpiNNaker 1 Million โ a machine with 1 million ARM processor cores (not one chip, 1,200,000 cores on 1,200 boards in 19 server racks, plus 7 tons of cables). Furber's idea was not "make it like a brain," but "give researchers a tool to run brain-scale brain models." SpiNNaker is neuromorphic by simulation, not by hardware: cores are standard ARM, spikes are modeled in software. Different school.
In August 2014 in Science appeared an IBM Research paper that defined the landscape for five years. "A Million Spiking-Neuron Integrated Circuit with a Scalable Communication Network and Interface" โ Paul Merolla, John Arthur, Rodrigo Alvarez-Icaza, Andrew Cassidy, Jun Sawada, Filipp Akopyan, Bryan Jackson and Dharmendra Modha's group presented TrueNorth: a chip with 5.4 billion transistors, 4,096 neurosynaptic cores, 1 million programmable neurons, and 256 million configurable synapses. The chip consumed 70 mW in operation (other measurements โ 63 mW) and processed 400ร240 pixel video at 30 fps, distinguishing pedestrians, cyclists, cars, and trucks. Dharmendra Modha called it "a supercomputer the size of a postage stamp, light like a feather, and low power like a hearing aid." Steve Furber in IEEE Spectrum commented: "The impressive aspects of TrueNorth are the integration density โ a million neurons on a single, admittedly very big, chip โ and the very low power consumption for this many neurons."
Technologically, TrueNorth went against what Mead did. Mead built analog neuromorphic circuits; TrueNorth was fully digital. Simple reason: analog suffers from process variation (each transistor differs slightly from its neighbor), and IBM made the chip in 28-nm Samsung process โ standard mobile technology used for iPhones. Digital in this sense was an engineering compromise: less "biological," but reproducible and scalable.
Intel entered the game later than IBM but went further. In September 2017 Intel Labs released Loihi โ research chip, 130,000 neurons and 130 million synapses on 14-nm FinFET, fully digital, with on-chip learning (spike-timing-dependent plasticity, STDP). In March 2020 Intel assembled Pohoiki Springs โ a system of 768 Loihi chips, 100 million neurons in one rack. In September 2021 came Loihi 2 โ 128 cores, 1 million neurons per chip, on-chip gradient-descent learning instead of STDP (critically important: SNNs can now be trained with backpropagation). In April 2024 Intel + Sandia National Laboratories launched Hala Point: 1,152 Loihi 2 chips, 1.15 billion artificial neurons, 128 billion synapses, in a microwave-sized enclosure. Sandia researcher Craig Vineyard said: "We believe this new level of experimentation โ the start, we hope, of large-scale neuromorphic computing โ will help create a brain-based system with unrivaled ability to process, respond to and learn from real-life data." Comparison with what Sandia received three years earlier (Pohoiki Springs, 50 million neurons): 10ร faster, 15ร denser, million circuits per chip.
Hala Point is already a production-class research system, not a "capabilities demo." Funding from NNSA (National Nuclear Security Administration, i.e., US nuclear shield), and that itself is telling: neuromorphic has shifted from exotic to a tool for solving "hard" problems where energy budget matters (drones, edge, real-time sensor stream processing).
And here begins the context in which APEX appears. After 2014 a split occurred in academia: some believed SNNs were a dead end because transformers won everything; others kept digging, and in 2022โ2026 their patience started paying off. ANN-SNN conversion (take trained ANN, convert to SNN, get spike equivalent that consumes less energy) โ this method has dominated recent years. QCFS activation (Quantization-Clip-Floor-Shift) โ standard technique for minimizing conversion error. But it has a fundamental problem: to match original ANN accuracy, converted SNNs need hundreds to thousands of timesteps, eating all savings from sparsity. PASCAL (2025) โ the work APEX builds on โ proposed the PASC-IF neuron, which mathematically provably reproduces QCFS activation in significantly fewer timesteps. At this moment APEX appeared as the first hardware design that efficiently supports PASC-IF without introducing sequential bottlenecks.
In June 2025 Sam Altman (OpenAI CEO) published a blog post revealing: the average ChatGPT query consumes 0.34 watt-hours. This is "about what an oven uses for just over a second, or an efficient lightbulb uses for a couple minutes," and 0.000085 gallons of water โ about 1/15 teaspoon. At first glance, 0.34 Wh is nothing. On second โ different arithmetic.
Altman added: "as data center production gets automated, the cost of intelligence should eventually converge to near the cost of electricity". He himself admits AI infrastructure is becoming electrical infrastructure. In February 2025 he wrote that "the cost of using AI will drop by 10 times every year," citing that price per token for GPT-4 in early 2023 vs GPT-4o in mid-2024 dropped 150ร โ "Moore's law on steroids." Pretty, but price per token drops not because hardware got more efficient, but because data centers got bigger and learned to batch queries better. Energy per inference drops slower than cost per token.
Enter arXiv 2505.09598 (How Hungry is AI? Benchmarking Energy, Water, and Carbon Footprint of LLM Inference, Abdelatti et al., published May 14, 2025, updated August 11, 2026). This is the first serious attempt at building an infrastructure-aware benchmarking framework for LLM inference. They took 30 modern models deployed in commercial data centers and calculated consumption per query through public API performance + regional environmental multipliers + statistical inference of hardware configs. Key findings:
Another critically important number: inference can account for up to 90% of total lifecycle energy consumption. Training is loud headline (for GPT-3 โ 1,287 MWh, 550 tons COโ, 700 kiloliters water for cooling, "two-thirds Olympic pool"), but inference is routine that in aggregate gives 10ร more than one-time training. Every improvement in energy efficiency per inference translates to linear savings for data centers.
In April 2026 the International Energy Agency published an update to its regular Energy and AI report: data center electricity consumption jumped sharply in 2025, despite mounting bottlenecks, and the industry entered a scramble for solutions. IEA previously forecast by 2030 data centers would consume 945 TWh โ roughly all of Japan's current generation. Hyperscalers already signing 20-year contracts for nuclear reactors: Microsoft + Constellation Energy (Three Mile Island, reactor being decommissioned, restarting for Microsoft), Google + Kairos Power (3 small modular reactors at 500 MW by 2035), Amazon โ acquiring Talen Energy (Cumulus Nuclear Plant, Pennsylvania).
In this context "โ40% energy on inference" is not abstract. If we can roll out an SNN accelerator delivering +40% efficiency only on edge workloads (and edge is smartphones, cameras, IoT sensors, wearables, robots, drones), the scale of savings over a decade runs into tens of GWh and billions in cooling infrastructure. APEX itself won't reach edge (40 nm is 2008, not flagship), but it proves the architecture works on synthesizable silicon, and now any fabless startup can take the APEX pattern and port to 7 nm.
Here begins the part the neuromorphic community doesn't like discussing, and which for me is most important in this whole story. In April 2026 on arXiv appeared "When Spike Sparsity Does Not Translate to Deployed Cost: VS-WNO on Jetson Orin Nano" (2604.17040), which put a fat period on one very comfortable illusion. Authors took the SNN architecture VS-WNO (Variational Sparsity โ Wavelet Neural Operator) and deployed it on NVIDIA Jetson Orin Nano โ real edge device costing $249, selling in millions. They found:
This doesn't mean SNNs are fraud. It means spike sparsity is necessary but not sufficient. Without specialized hardware that efficiently skips zero spikes at gate level (not "programmatically check if zero"), you pay overhead for spikes without getting benefits. APEX is precisely that "specialized hardware" solving this problem at hardware level, not "library level on top of CUDA." That's why work like APEX is not academic exercise but the only way to make spike savings actually deployable.
Second limitation, pointed out by Jason Eshraghian (UC Santa Cruz, one of the leading young-generation SNN researchers) in EE Times interview (July 18, 2025): "I think people need to be comfortable with shaking the neuromorphic branding a little bit, being OK with the fact that binary spikes aren't the perfect representation." His group developed SpikeGPT โ generative language model at 216M parameters, implemented as SNN โ and found that scaling to 1 billion parameters accuracy gains become marginal because binary spikes (amplitude 0 or 1) compress information too much. Backpropagation works poorly with encoding information in spike timing rather than amplitude. The solution Loihi 2 and APEX apply โ limited spike amplitude (multi-bit spikes), i.e., "loosen neuromorphic branding, allow spikes to have multiple levels." Essentially, return to analog behavior in digital wrapper, and this is the most interesting direction currently in the industry.
No serious person in the neuromorphic community says "SNNs will kill NVIDIA." Mike Davies (director of Neuromorphic Computing Lab at Intel Labs) back in 2020 at Intel Labs Day said directly: "There's confusion about neuromorphic research, because there's an overlap between what we can run on a neuromorphic chip like Loihi, and what these deep learning models do." That is, Loihi runs both ANNs and SNNs, and ANNs on it are not "native" workload but converted through special frameworks (Nengo, Lava, NxCore).
Real application zone for SNNs โ event-driven workloads (incoming data already sparse and asynchronous), edge inference (where watts matter), real-time sensory processing (where latency trumps throughput), always-on (where device sits on battery for years). That is:
BrainChip Holdings (ASX: BRN, Australian fabless) โ the only purely commercial company selling neuromorphic chips under the Akida brand. In May 2025 BrainChip published updated Technology Roadmap, and in May 2026 โ Investor Update at AGM 2026. Akida chips sit in several commercial products (mainly smart home IoT, security cameras, industrial sensors), but BrainChip revenue remains laughable by semiconductor industry standards โ single-digit millions per quarter, losses, share dilutions. Neuromorphic is not investment but R&D bet, and the commercial curve hasn't reached operating profit yet.
Still โ BrainChip, Akida, IP cores, ready neural models, MetaTF dev tools, reference platforms, Akida Cloud โ this is no longer "scientific prototype," this is product line. The cycle from Carver Mead (1989) to real neuromorphic IP core licensed and integrated into SoCs โ 36 years. Very long, but it happened. In semiconductors everything takes long.
Parallel track many miss โ IBM NorthPole. In February 2024 at ISSCC 2024 IBM presented NorthPole โ 12-nm chip optimized for neural network inference. This is not neuromorphic in pure sense (not spiking, not event-driven), but in-memory computing: computation happens directly in SRAM, without moving data between memory and compute units. By IBM benchmarks, NorthPole delivers ร25 energy efficiency and ร22 speed vs GPU at same process node on several workloads (real-time object recognition, NLP tokenization). This is different branch of alternative hardware โ not spiking but in-memory compute โ evolving in parallel. NorthPole is next step between classic GPU and neuromorphic, and IBM's main commercial AI hardware bet.
APEX came out August 21, 2026, and timing is not accidental. Look at parallel events:
Not convergence โ systemic shift: the academic community prepared SNN hardware for 36 years, and in 2026 several reasons simultaneously (energy, regulation, data center capex, edge demand, political bets on AI sovereignty) make it relevant.
In 2024โ2025 TU Dresden (Steve Furber continues collaborating with them) began deploying SpiNNaker-2 โ second-generation machine promising ร10 performance vs SpiNNaker 1 at same power consumption. SpiNNaker-2 is different philosophy: not "chip with neuromorphic circuits" but "array of regular ARM cores optimized for spike traffic." This is neuromorphic as system-level architecture, not circuit-level architecture, and the approach bears fruit: SpiNNaker-2 already used for modeling full mouse brain (70 million neurons) under EBRAINS (EU Human Brain Project successor).
Prophesee (French startup, founded 2014) and iniVation (Switzerland, grew from iniLabs and Misha Mahowald Prize) make event-based cameras outputting asynchronous spike streams instead of frames. On such cameras regular GPU processes data at 5โ10% efficiency (95% events are noise and zeros), while neuromorphic chip โ at 80โ90% (anything not a spike simply isn't touched). Prophesee in 2024 raised Series C โฌ50 million and sells sensors for automotive ADAS, industrial inspection, AR/VR. If APEX-like chips become standard, event cameras get ideal native target โ symbiosis that didn't exist for 30 years.
The APEX paper itself doesn't discuss three things critical for practice:
APEX is honest work. No marketing noise, no exaggeration, no attempt to sell "next revolution in AI." Authors say: "on ResNet18 we give โ40% energy at better accuracy; on AlexNet and VGG16 โ small energy penalty but +2% accuracy." This is engineering language, not "Silicon Valley pitch."
What I like about APEX architecturally โ eliminating sequential bottleneck. PASC-IF neuron is three-stage, and naively implemented "step-by-step" would kill the parallelism FTP dataflow provides. APEX solves this by unpacking all three stages into combinational circuits โ latency doesn't add, area grows 2.7%, power 1.3โ5.4%. This is exactly the type of solution that in hardware engineering is called "free lunch": you get qualitative leap in accuracy almost free. In a world where every milliwatt-hour at data centers counts, 2.7% area is fair price for eliminating 1024 timesteps to 8โ16.
What concerns me about APEX โ narrow experimental base. Authors test ResNet18, AlexNet, VGG16 on classic image classification benchmarks. Very 2017. Modern SNNs must prove themselves on transformer-like workloads, graph neural networks, reinforcement learning, on-device personalization (online learning without retraining). APEX is silent here. Means production deployment still 3โ5 years minimum: first tape-out, characterization, then software stack, then at least one workload beyond classification, then pilot in Prophesee edge camera or hearing aid, then โ if lucky โ SoC integration.
Still โ APEX stands in the right place in 2026. Not as "NVIDIA killer" but as proof of concept for an entire class of architectures that existed on the margins for 36 years and now quietly become relevant. Stakeholders at every level: Intel (Hala Point), IBM (NorthPole), BrainChip (Akida), Prophesee (event cameras), iniVation (sensors), academia (APEX, PASC-IF, SpikeGPT, SpiNNaker-2) โ all moving in one direction, and this direction for the first time in a decade aligns with economic incentive.
Most beautiful irony โ the brain, for which this all started, remains beyond comparison. Human brain โ 86 billion neurons, 20 watts, 20 Hz average spike frequency. Hala Point โ 1.15 billion neurons (1.3% of brain) but consumes **2,600 W** (130ร more than brain per neuron). APEX at 16 TPPEs โ tens of thousands of neurons, million times smaller than brain, tens of milliwatts. Progress exists, but orders of magnitude still not in our favor. Carver Mead in 1989 said in 20 years hardware would replicate the brain. In 2026 we're still on that path, and APEX is one small brick on it. But the brick is synthesizable, synthesis passes at 400 MHz, and the brick factory is already under construction.